1. Field of the Invention
The present invention relates to a push-pull amplifier circuit and an operational amplifier circuit using the same.
2. Description of Related Art
FIG. 7 shows a push-pull amplifier circuit 1 disclosed in Japanese Unexamined Patent Application Publication No. 2002-261550 as prior art. As shown in FIG. 7, the push-pull amplifier circuit 1 includes constant current sources I1 to I3, NMOS transistors M1 to M5 and M8, a depletion-type NMOS transistor M6, PMOS transistors M7 and M9, resistors R1 to R3, a signal input terminal TIN, and a signal output terminal TOUT. The NMOS transistors M1 to M5 and M8 and the PMOS transistors M7 and M9 are enhancement-type MOS transistors. Note that reference symbols “I1” to “I3” denote constant current sources as well as currents output from the constant current sources and current values thereof.
The operation of the push-pull amplifier circuit 1 will be described. First, consider a case that voltage Vin of the input signal supplied to the signal input terminal TIN (hereinafter, referred to as “input voltage”) decreases. When the input voltage Vin decreases, drain currents IM7 and IM9 of the PMOS transistors M7 and M9 increase. The NMOS transistors M5 and M4 constitute a current mirror. Thus, when the drain current IM7 increases, a drain current IM4 of the NMOS transistor M4 also increases. When the drain current IM4 increases, a gate-source voltage V1 of the NMOS transistor M8 decreases. As a result, the drain current of the NMOS transistor M8 decreases. Accordingly, an output voltage Vout of the signal output terminal TOUT increases.
Next, consider a case that the input voltage Vin supplied to the signal input terminal TIN increases. When the input voltage Vin increases, the drain currents IM7 and IM9 of the PMOS transistors M7 and M9 decrease. When the drain current IM7 decreases, the drain current IM4 of the NMOS transistor M4 also decreases. When the drain current IM4 decreases, the gate-source voltage V1 of the NMOS transistor M8 increases. As a result, the drain current of the NMOS transistor M8 increases. Accordingly, the output voltage Vout of the signal output terminal TOUT decreases.
In this way, the push-pull amplifier circuit 1 makes the drain currents of the PMOS transistor M9 and the NMOS transistor M8 vary according to the input voltage Vin. The PMOS transistor M9 and the NMOS transistor M8 constitute a current path for an output stage of the push-pull amplifier circuit 1. Accordingly, the push-pull amplifier circuit 1 operates push-pull output function on output current Tout. Regard that a portion composed of the constant current sources I1 to I3, the NMOS transistors M1 to M3, and the resistors R1 and R2 is designed so that the appropriate gate-source voltage V1 is applied to the NMOS transistor M8 when the value of the output current Iout (source direction is defined as positive) flowed from the signal output terminal TOUT is zero. The value of the output current Iout flowed from the signal output terminal TOUT is zero means that the drain current values of IM8 and IM9 are equal (IM9=IM8).
Now, consider a case that the input voltage Vin is further decreased so as to further increase the output current Iout or further increase the output voltage Vout in the operation of the push-pull amplifier circuit 1. When the input voltage Vin decreases, the drain current IM9 increases and the drain current IM7 also increases. As the drain current IM7 increases, the drain current IM8 decreases. Then, the voltage Vout increases. When the output voltage Vout is close to a power supply voltage VDD, the drain-source voltage of the PMOS transistor M9 decreases. This makes the PMOS transistor M9 operate in a linear region and contribute less to increase of the drain current IM9 even if the input voltage Vin is greatly decreased. Therefore, further decrease in the input voltage Vin does not effect further increase in the output current Tout or the output voltage Vout. In such a case, the NMOS transistor M6 and the resistor R3 suppress the upper limit value of the drain current IM7 of the PMOS transistor M7, thereby reducing power consumption of the push-pull amplifier circuit 1. This effect is based on the operation principle of the push-pull amplifier circuit 1 as described below.
To explain the above-mentioned effect, assume a configuration of the push-pull amplifier circuit 1 in which the NMOS transistor M6 and the resistor R3 are omitted. First, since the NMOS transistor M5 operates as a MOS diode, the drain voltage V2 of the NMOS transistor M5 would be approximately slightly higher than the threshold voltage, for example, about 1.0 V. Assuming that the power supply voltage VDD is 3.0 V, the drain-source voltage of the PMOS transistor M7 is about 2.0 V. Such a voltage is generally sufficient for the PMOS transistor M7 to operate in the saturated region. Accordingly, if the input voltage Vin is decreased, the drain current IM7 further increases and this leads increase in wasteful current consumption while an increase in the output current Iout is not gained.
In the push-pull amplifier circuit 1, the NMOS transistor M6 is a depletion-type transistor which is self-biased by the drain current with the resistor R3 the NMOS transistor M6 is suppressed flowing drain current under normally-on where the gate-source voltage is zero or less. Therefore, the upper limit value of the drain current IM7 is controlled and an increase in wasteful current consumption is prevented.